1. Field of the Invention
The present invention relates to a semiconductor integrated circuit equipped with an output circuit for serving as an interface of a digital circuit, which operates with different electricity source voltages.
2. Description of Related Art
The finer the structure of a MOS transistor becomes, the weaker the strength of a gate oxide film becomes. For example, a MOS transistor produced in a fine process of an extent of 0.35 μm, is able to operate with an electricity source voltage of an extent of 3.3V. Further, MOS transistor produced in a latest fine process of an extent of 0.18 μm, is able to operate with an electricity source voltage of an extent of 1.8V. In order to make an interface with a circuit of 0.35 μm fine process, both of a MOS transistor able to be connected with an electricity source voltage of an extent of 1.8V and a MOS transistor able to be connected with an electricity source voltage of an extent of 3.3V are formed in a circuit of 0.18 μm fine process of the conventional art, so as to transform signal level from 1.8V to 3.3V. This the signal level transforming circuit includes an output circuit.
(First Prior Art)
FIG. 13 is a circuit diagram showing a structure of a level transforming circuit of a first prior art disclosed in Japanese patent publication No. 6-216752. This level transforming circuit comprises with MOS transistors which have a dielectric strength of a gate oxide film that is lower than a high voltage (5V), so as to transform level from a low voltage electricity source system to a high voltage electricity source system. As shown in FIG. 13, this level transforming circuit comprises a level transforming section comprising MOS transistors 300 to 313, and an output section comprising MOS transistors 314 to 317. The level transforming section has input there to the signal a IN of low voltage (VCC:3V) electricity source system, so as to output a signal for transforming a level to node N21, N22. The output section has input thereto a control signal from the level transforming section mentioned above, so as to output an output signal OUT1 having an amplitude of 0V to 5V as a signal of a high voltage (VDD:5V) electricity source system, an output signal OUT2 having an amplitude of an intermediate electric potential to 5V as a signal of the same, and an output signal OUT3 having an amplitude of 0V to an intermediate electric potential as a signal of the same.
Here, described is an occasion when an output enable signal OE and its inverse signal OEB are inputted with the H level and the L level respectively. If input signal IN becomes the L level, PMOS 306, 307 turns on and NMOS 305, 312 turns off. As a result, node N23, N24 becomes the H level, and NMOS 304 turns on. Then, a source electric potential of NMOS 302 decreases, and a route of current comprised of NMOS 302, PMOS 301 is taken. On the other hand, node N25 is pulled down, and, PMOS 308 turns on. When PMOS 308 turns on, node N21 becomes the H level, and, PMOS 309 turns on. Then, drain electric potential of NMOS 310 is pulled up to the high voltage VDD. Moreover, when node N24 becomes the H level, NMOS 311 is on, because the output enable signal EB is the H level. Then, node N22 becomes H level, and output signal OUT3 becomes 0V. When node N21 becomes the H level, PMOS 314 turns off, and output signal OUT2 becomes an intermediate electric potential. Output signal OUT1 becomes 0V, as NMOS 316 turns on, because output signal OUT3 is 0V.
On the other hand, if input signal IN becomes H level, NMOS 305, 312 turns on and PMOS 306, 307 turns off. Then, the electric potential of nodes N22, N23 are pulled down, and NMOS 317 turns off. Since NMOS 311 is on, node N24 is pulled down, and a route of current comprised of PMOS 309, NMOS 310 is taken, and PMOS 314 turns on, when node N21 is pulled down, and PMOS 300 turns on, so as to pull up node N25, Output signal OUT1 becomes 5V, output signal OUT2 becomes 5V, and output signal OUT3 becomes an intermediate electric potential.
(Second Prior Art)
FIG. 14 is a circuit diagram showing a structure of a level transforming circuit of a second prior art disclosed in Japanese patent No. 3258229. This level transforming circuit comprises MOS transistors which have a dielectric strength of gate oxide film that is lower than a high voltage (5V), so as to transform a level from a low voltage electricity source system to a high voltage electricity source system, similar to the first prior art. As shown in FIG. 14, this level transforming circuit comprises CMOS circuit 410, intermediate circuit 430, 440, and CMOS circuit 420.
CMOS circuit 410 comprises PMOS 411, 412 and NMOS 413, 414. PMOS 411, 412 are connected in series between the high voltage electricity source (VDD: 5V) and output node N1. NMOS 413, 414 are connected in series between the node N1 and the ground. The gate of PMOS 411 for pulling up is connected with node N4. On the other hand, the gate of NMOS 414 for pulling down has input thereto inputted with a signal IN which amplitude is between a low voltage (VCC:3V) and the ground. On the other hand, each gate of PMOS 412 and NMOS 413 is impressed with the low voltage in common.
The intermediate circuit 430 comprises PMOS 431, 432. PMOS 431 is connected between the high voltage electricity source VDD and output node N3, and its gate is connected with node N4. On the other hand, PMOS 432 is connected between node N3 and the low voltage electricity source VCC. and its gate is connected with output node N1 of CMOS circuit 410.
The intermediate circuit 440 comprises PMOS 441, 442. PMOS 441 is connected between the high voltage electricity source VDD and output node N4, and its gate is connected with node N3. On the other hand, PMOS 432 is connected between node N4 and the low voltage electricity source VCC, and its gate is impressed with output signal OUT1.
CMOS circuit 420 comprises PMOS 421, 422 and NMOS 423, 424. PMOS 421, 422 are connected in series between the high voltage electricity source VDD and output node N2. NMOS 423, 424 are connected in series between the output node N2 and the ground. The gate of PMOS 421 for pulling up is connected with node N3. On the other hand, the gate of NMOS 424 for pulling down, is inputted with an inverse signal of the input signal IN. On the other hand, each gate of PMOS 422 and NMOS 423 is impressed with the low voltage VCC in common.
Hereafter, the operation of this circuit is described.
When the input signal IN is the low voltage level VCC, NMOS 414 turns on, and PMOS 432 turns on. As a result, PMOS 441, 421 turn on. On the other hand, NMOS 424 turns off by the inverse signal of the input signal, and PMOS 442 turns off. Therefore, an output signal of the high voltage level VDD is output to OUT1. In this state, direct current does not pass through the circuit, because PMOS 411, 431, 442 and NMOS 424 are in the off state.
On the other hand, when the input signal changes from the low voltage level VCC to the ground level (0V level), NMOS 424 turns on, and PMOS 442 turns on. As a result, PMOS 411, 431 turn on, and NMOS 414 turns off by the inverse signal of the input signal. Then, PMOS 432 turns off. Therefore, an output signal of the ground level (0V level) is output. In this state, direct current does not pass through the circuit, because PMOS 421, 441, 432 and NMOS 414 are in the off state.
FIG. 15 is a circuit diagram showing the structure of a three state output circuit equipped with the level transforming circuit mentioned above. The logic circuit of the low voltage electricity source system has a data terminal 451 and an enable terminal 452, and it comprises a NAND gate 453, inverters 454, 455, and a NOR gate 456. Further, with the output side of said level transforming circuit, connected is a pre-buffer circuit 460, and with this, connected is a main buffer circuit 470. The pre-buffer circuit 460 comprises PMOS 461, 462, and it provides PMOS 471 with a signal having an amplitude between the high voltage VDD and the low voltage VCC. On the other hand, the main buffer circuit 470 comprises PMOS 471, 472 and NMOS 473, 474, and outputs an output signal OUT from an output pad 480 to the outside of the integrated circuit.
When the ground level 0V is inputted to the enable terminal 452, the high voltage level VDD is impressed with the gate of PMOS 471 and the ground level 0V is impressed with the gate of NMOS 474. Then, the output signal OUT becomes a high impedance state.
On the other hand, when the low voltage level VCC is impressed with the enable terminal 452 and the low voltage level VCC is impressed with the data terminal 451, the low voltage level VCC is impressed with the gate of PMOS 471 and the ground level 0V is impressed with the gate of NMOS 474. Then, the output signal OUT becomes the high voltage level VDD.
Moreover, when the low voltage level VCC is impressed with the enable terminal 452 and the ground level 0V is impressed with the data terminal 451, the high voltage level VDD is impressed with the gate of PMOS 471 and the low voltage level VCC is impressed with the gate of NMOS 474. Then, the output signal OUT becomes the ground level 0V. Therefore, the three state buffer circuit functions.
However, the output circuit of the conventional art mentioned above has the following problems.
Transistors operating with the low voltage electricity source and transistors having a gate oxide film strength stronger than the voltage level VDD of high voltage electricity source, must be formed together. Therefore, the gate oxide films of some transistors must be thick and their gate length must be long, and this kind of MOS transistors available for the output circuit, must be formed partially on some portions of an integrated circuit on a semiconductor chip. Thus, there is a problem that the manufacturing process becomes complicated.
Moreover, as for the first prior art (FIG. 13), an output circuit is able to comprise only transistors having a gate oxide film strength lower than the high voltage level VDD. However, the first prior art limits the amplitude of a gate voltage (node N21) of PMOS 314, by using the effect of turning off PMOS 309, so as to restrain the gate voltage under the strength of gate oxide film less than the high voltage level VDD. Meanwhile, the gate of PMOS 309 is impressed with an electric potential VB. Therefore, the electric potential of the gate of PMOS 309 does not decrease less than VB+Vth, even if a logical value of node N21 is the L level. Here, Vth is threshold voltage of PMOS.
While PMOS 309 is turning off, the electric potential of node N1 gradually comes to VB+Vth. The level transforming circuit of the first prior art uses this motion. Thus, there is a problem that it cannot operate rapidly.
Moreover, the gate voltage of PMOS 314 (electric potential of node N21) becomes VDD−(VB+Vth). So, if (VB+Vth) is higher than 3V, the gate voltage becomes a low value. Therefore, there is another problem that the ability to a bear load of the output section decreases. Moreover, the output signal OUT1 rises to 5V from 0V, when NMOS 317 turns off and PMOS 314 turns on. In this occasion, the source electric potential of PMOS 315 is pulled up rapidly. Therefore, the voltage Vgs between gate and source of PMOS 315 becomes certain voltage, so that the current flowing in PMOS 315 is equal to the current flowing in PMOS 314. So, between the source and drain of PMOS 315, voltage of VCC+Vgs is impressed. Similarly, output signal OUT1 drops to 0V from 5V, when PMOS 314 turns off and NMOS 317 turns on. In this occasion, the source potential of NMOS 316 is pulled down rapidly. Therefore, the voltage Vgs between the gate and source of NMOS 316 becomes a certain voltage, so that the current flowing in NMOS 316 is equal to the current flowing in NMOS 317. So, between source and drain of NMOS 316, voltage of VCC+Vgs is impressed. Therefore, voltage exceeding the voltage preferred in a low voltage electricity source system, is transiently impressed between the source and drain. Thus, the ability of the device is deteriorated by a hot carrier. As a result, a problem is caused that the reliability of the device deteriorates.
Moreover, as for second prior art (FIG. 14, 15), an output circuit is able to comprise only transistors having a gate oxide film strength lower than the high voltage level VDD, as well. However, the second prior art has the following problem.
When the enable terminal 452 is impressed with the low voltage level VCC, the data terminal 451 becomes the ground level VCC from the low voltage level VCC. In this occasion, the gate voltage of PMOS 471 becomes the high voltage level VDD from the low voltage level VCC, and the gate voltage of NMOS 474 becomes the low voltage level VCC from the ground level. As a result, the output signal OUT becomes the ground level from the high voltage level VDD. In this occasion, in order to bear a load connected to the output pad 480, the voltage between the source and drain of NMOS 473 becomes VDD−VCC+Vgs. Here, Vgs is the gate source voltage of NMOS 474, which flows current in NMOS 473 the same as current flowing in NMOS 474. So, the voltage between the source and drain transiently becomes higher than VCC. Similarly, the voltage between the gate and source of PMOS 472 becomes VCC+Vgs. Here, Vgs is gate source voltage of PMOS 472, which flows current in PMOS 472 the same as current flowing in PMOS 471. So, the voltage between the source and drain transiently becomes higher than VCC. Therefore, voltage exceeding the voltage preferred in low voltage electricity source system, is transiently impressed between source and drain. Moreover, voltage exceeding the voltage preferred in a low voltage electricity source system, is transiently impressed between the gate and source. Thus, the ability of the device is deteriorated by a hot carrier. As a result, a problem is caused that the reliability of the device deteriorates.
Moreover, with dropping of output node N3, output node N2 is pulled up by the turning on current of PMOS 421 flowing through PMOS 422. As shown in FIG. 15, a buffer to drive succeeding output stage is provided to the level transforming circuit. This buffer comprises two PMOS 461, 462, which are connected in series between the high voltage electricity source VDD and the low voltage electricity source VCC. The source of PMOS 461 is connected with the high voltage electricity source VDD. The drain of PMOS 462 is connected with the low voltage electricity source VCC. The gate of PMOS 461 is connected with output node N3. The gate of PMOS 462 is connected with output node N2. Therefore, PMOS 461 comes into on state, while PMOS 462 is still in on state. Therefore, passing current flows from the high voltage electricity source VDD to the low voltage electricity source VCC. As a result, a problem is caused of increasing electricity consumption in vain.
Moreover, as described in Japanese patent 3258229, in the occasion when the output stage of a semiconductor integrated circuit is driven, each transistor of the output stage usually has a gate width of several hundreds μm. So, as for gate the width of each transistor of a buffer driving this transistor of the output stage, if it is narrower than several hundreds μm, current flowing through the output stage decreases. As a result, a problem is caused of decreasing the drivability of the output stage.
The present invention is aimed at providing a novel and improved semiconductor integrated circuit, which is able to operate fast and to restrain drivability drop, so as to solve the problems contained in the semiconductor integrated circuit of the prior art mentioned above.